Cyclone 10 GX Transceiver PHY in PCS Direct vs Enhanced

HI Etienne,

When you use "PCS Direct" mode, you basically bypass most of the PCS block function.

However when you enable "basic enhanced" mode, certain PCS block function is enabled depends on what PCS block and how you enable and configure them in NativePHY IP accordingly.

Feel free to checkout below guideline to find out more about PCS block usage.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf

Thanks.

Regards,

dlim

Hi dlim

Thank you very much for your answer.

At this stage, the reason why I want to use the Enhanced PCS (as compared to the Direct PCS) is the possibilty to have a fifo between pma and the fpga fabric. To do so, I choose the following options in the Transceiver PHY IP editor:

• Transceiver configuration rules : Basic (Enhanced PCS)
• Data rate : 5250
• Enhanced PCS/PMA interface Width : 64
• FPGA/FAbric/ Enhanced PCS interface Width : 64
• TX FIFO Mode : Phase Compensation (for both tx and rx)

All the other parameters of the Enhanced PCS are the default values given in the IP editor

The data I get at the tx serial port (observed with a high speed oscilloscope) is always a continuous sequence of 111110001111100011111000.... whatever the data set at the parrallel port.

The data I get at the rx parralel port is a constant.

I set the tx_control register to 2'b01 but I not sure to understand the usefullness of that tx_control register. In any case whatever the value I have, I get the same pb.

I don't use "dynamic reconfiguration".

Thank you for your help !

Best regards

Etienne

HI Etienne,

The tx_control register is used to tell whether current bit sent belongs to control bit or data bit.

Anyway, looks like in your case, you can't send out data properly in your Tx channel and you also can't receive back expected data in your Rx channel.

I would recommend to start with basic debug first like pls check FPGA power connection on board and also your transceiver design reset and clocking pins as per below pin connection guideline doc.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf

Once you rule out there is no issue with your board then you can check at your Quartus design. Feel free to start with referring to some reference design to get something working first then you can slowly enable your desired setting in NativePHY IP. If it failed then you will know which setting is causing the issue.

• https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/
• https://fpgawiki.intel.com/wiki/Cyclone10_Transceiver_PHY_Basic_Design_Examples
• https://fpgawiki.intel.com/wiki/Arria10_Transceiver_PHY_Basic_Design_Examples

Your goal is to ensure you can send data correctly out from Tx channel first, after that you can move on to debug Rx channel.

For Rx channel, check the CDR lock status first by looking at the cdr_lockedtodata pin. If it failed then you can refer to attached CDR debug guideline.

Thanks.

Regards,

Deshi

The probleme is now solved: the pll_locked signal coming from the ATX PLL was not connected to the PHY Reset controller. Witout this pll_locked signal, the Transceiver was working well in a PCS direct mode but not in the PCS Enhanced mode.

Thank you for your help

Great ! Hopefully everything go well with the rest of your project development