Cyclone 10 GX Transceiver PHY in PCS Direct vs Enhanced

HI Etienne,

The tx_control register is used to tell whether current bit sent belongs to control bit or data bit.

Anyway, looks like in your case, you can't send out data properly in your Tx channel and you also can't receive back expected data in your Rx channel.

I would recommend to start with basic debug first like pls check FPGA power connection on board and also your transceiver design reset and clocking pins as per below pin connection guideline doc.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf

Once you rule out there is no issue with your board then you can check at your Quartus design. Feel free to start with referring to some reference design to get something working first then you can slowly enable your desired setting in NativePHY IP. If it failed then you will know which setting is causing the issue.

• https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/
• https://fpgawiki.intel.com/wiki/Cyclone10_Transceiver_PHY_Basic_Design_Examples
• https://fpgawiki.intel.com/wiki/Arria10_Transceiver_PHY_Basic_Design_Examples

Your goal is to ensure you can send data correctly out from Tx channel first, after that you can move on to debug Rx channel.

For Rx channel, check the CDR lock status first by looking at the cdr_lockedtodata pin. If it failed then you can refer to attached CDR debug guideline.

Thanks.

Regards,

Deshi