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jsnow8's avatar
jsnow8
Icon for New Contributor rankNew Contributor
5 years ago

Cyclone 10 GX transceiver bank cannot be fully utilized

Hi,

I am trying to compile a design, with 6 TSE MACs, going as SGMII connections to PHYs, in the Cyclone 10 GX. Everything was working fine up to 5 MACs (~30% device utilization), whereas 6 MACs give me errors in the Fitter where "Fitter requires XX LABs for clock region in locations from lower-left (1,1) to upper right (37,31) but only YY LABs are available...". I have around 10 of these errors.

The design is approximately at 40% utilization. Global clocks are set.

I have tried setting the fitter to ignore timing (the only way to compile), and it gives timing issues for registers inside the MACs which I do not know how to debug. There is seemingly no user created signal which violates timing.

In terms of clocks, I am using an ATX PLL, with the MCGB turned on.

Running the chip planner, and looking at routing - I see regions with 110% utilization, whereas there is 60% of the chip which is empty.

Please advise

4 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    TSE MAC is a soft IP which means it's utilizing FPGA core logic to build the IP and it also needs to placed closer to the transceiver channel to ease the design timing closure.

    • FPGA utilization report just reported out total logic utilization in your design but it doesn't show you where the location all these logic are used up.
    • Relaunch your 5 TSE MAC design then you can use Quartus "chip planner" feature to open up the GUI view to show you roughly where all FPGA logic utilization are consumed. I suspected it's all crowded at one corner region that caused the Quartus fitter compilation error

    Well, in case you wonder why Quartus doesn't use the empty logic resource on other corner of the FPGA, this is because

    • It doesn't make sense for example to use transceiver channel pin on left side of the FPGA and fitter place TSE MAC IP on the right side of FPGA where the data bus needs to travel all the way from right to left of the FPGA. We always wanted the shortest path transmission for ease of design timing closure

    My suggestion to you is

    • Use transceiver pins on other bank/side of FPGA (if available) so that Quartus fitter will place the 6th TSE MAC IP at other unused region of FPGA
    • or switch to use "LVDS" instead of "GXB" option in TSE IP to use LVDS pins on other corner bank of FPGA unused region
    • Last resort is unfortunately to use a bigger Cyclone 10 GX FPGA capacity device with more FPGA core logic resources

    Thanks.

    Regards,

    dlim

    • jsnow8's avatar
      jsnow8
      Icon for New Contributor rankNew Contributor
      5 years ago

      Thank you!

      The bulk of the logic is in the Left corner, and some of the registers associated with the MACs are in the left middle section of the device - above (31,37). It is crowded as you suspected.

      I am using a single transceiver bank device.

      Are there any alternatives to using the TSE MAC which can be more resource friendly?

      • Deshi_Intel's avatar
        Deshi_Intel
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        HI,

        You can try turn off some unused feature in TSE MAC IP setting but I am not sure how much saving you can get out of it.

        Or pls consider to use LVDS instead of GXB as I suggested earlier.

        Worst case would be to use bigger FPGA device.

        Thanks.

        Regards,

        dlim

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    I am setting this case to closure since I haven't hear back from you for quite sometime after my June feedback.


    Feel free to post new forum thread if you still have new enquiry in future.


    Thanks.


    Regards,

    dlim