Cyclone 10 GX transceiver bank cannot be fully utilized

Hi,

TSE MAC is a soft IP which means it's utilizing FPGA core logic to build the IP and it also needs to placed closer to the transceiver channel to ease the design timing closure.

• FPGA utilization report just reported out total logic utilization in your design but it doesn't show you where the location all these logic are used up.
• Relaunch your 5 TSE MAC design then you can use Quartus "chip planner" feature to open up the GUI view to show you roughly where all FPGA logic utilization are consumed. I suspected it's all crowded at one corner region that caused the Quartus fitter compilation error

Well, in case you wonder why Quartus doesn't use the empty logic resource on other corner of the FPGA, this is because

• It doesn't make sense for example to use transceiver channel pin on left side of the FPGA and fitter place TSE MAC IP on the right side of FPGA where the data bus needs to travel all the way from right to left of the FPGA. We always wanted the shortest path transmission for ease of design timing closure

My suggestion to you is

• Use transceiver pins on other bank/side of FPGA (if available) so that Quartus fitter will place the 6th TSE MAC IP at other unused region of FPGA
• or switch to use "LVDS" instead of "GXB" option in TSE IP to use LVDS pins on other corner bank of FPGA unused region
• Last resort is unfortunately to use a bigger Cyclone 10 GX FPGA capacity device with more FPGA core logic resources

Thanks.

Regards,

dlim