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epissadakis's avatar
epissadakis
Icon for New Contributor rankNew Contributor
8 months ago

Cyclone 10 GX continiously increasing power consumption

Hello,

We developed two custom evaluation boards (different layouts) using the Cyclone 10CX150YU484E5G FPGA .

Our problem is that we face the same increasing power consumption issue in both development boards.

Before and after the FPGA placement we measured all the point of loads on the PCB and there was no short circuit. The FPGA is biased correctly in every pin. We also followed the guidelines for the power-up sequence.

After placing the FPGA we stated the following issues:

1.The un-programmed FPGA increased gradually the current consumption of the boards and it was also heated a lot.

2. Before the FPGA programming the GPIOs of all the banks outcome "high" values.

3.After the successful FPGA programming through JTAG and AS the rate of the current consumption dramatically increased.

Do you have any ideas regarding the cause of this behavioral in any of the above mentioned issues ?

Regards,

5 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor

    Hello,


    Are you able to check if there is connection leakage(shorted) between VCC and GND somewhere on the PCB?


    regards,

    Farabi


    • epissadakis's avatar
      epissadakis
      Icon for New Contributor rankNew Contributor

      Hello,

      We checked it and seems that there is no connection leakage between VCC and GND.

      We cannot understand why in an un-programmed FPGA all the pins are in logic "high" .

      Could this cause the increasing power consumption ?

      Regards

      Manolis

  • Hi,


    Can you test by using power analyzer tool to see which part show high power consumption?


    Regards,

    Aiman


  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor

    Hi,
    - having GPIO pulled high (by weak pull-up resistor in 10k range) in unconfigured state is regular behaviour, just read the manual. Also unused pins are equipped with weak pull-up by default, different behaviour can be however assigned in device and pin options.

    - FPGA current consumption is mainly caused by dynamic losses. Respectively it depends on clock frequency and amount of switching registers, in other words - on your design. It's usually higher in configured state.

    There are nevertheless many ways to achieve excessive current consumption by hardware design faults, particularly for a FPGA like Cyclone 10 GX that has power sequencing requirements.

    we don't yet know what is "dramatical increase" for you, e.g. what's the FPGA package temperature rise?

    Regards
    Frank

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