Cyclon V performance

It is impossible to give a rule of thumb based only on logic utilization. You can make a very slow system that uses 1% of the FPGA just like a highly optimized and fast system that uses 90%. It is really depending on the design, mostly on what kind of resources are used and the level of pilelining. The main factor will probably be the highest number of LUTs /DSP blocks/memory cells you have in series between two clocked registers.

Given that it is already hard to go over 150MHz in a Cyclone IV without heavy pipelining and optimisation, I wouldn't bet on 250MHz on the Cyclone V.

Just compile your design in Quartus and see what Timequest says.

This question is a bit like saying “I have a C program that’s 100 lines of code, but I won’t tell you what those lines are. How many processor cycles will the program use, given that amount of code?”

I can make a simple Cyclone IV design that fills 40% of an FPGA and runs at 400 MHz. I could also make a complex design that fills 40% but can’t go over 1 MHz. The utilization means little without the context of what the design is doing.

However, some functional blocks do have speed limits that are helpful to understand. If part of your design uses memory blocks, that part will be limited to the maximum speed of those memory blocks. The same goes for multiplier/DSP blocks and the clock networks that feed the part.

Pulling a couple numbers from data sheets, the fastest speed grade Cyclone IV has these attributes:

18x18 multiplier – 287 MHz max

Single-port 256x36 memory block – 315 MHz max

Cyclone V, in contrast, has these attributes:

18x18 multiplier – 287 MHz max

Single-port memory block (any width) – 315 MHz max

Those are not mistyped; Altera really did not improve these specs according to their current data sheets. Instead, they improved the FPGA architecture to handle complex operations better. For example, the Cyclone V DSP blocks can do a 27x27 multiply and add useful functionality like filter coefficient storage. The new logic element structure with wider LUTs can break large blocks of combinational logic down into fewer sections, which means complex operations will resolve faster. MLABs can replace memory blocks for small amounts of memory, and those can run at 450 MHz.

So, if you have a design that is optimized for the Cyclone IV architecture, you may not see much of a difference on Cyclone V. However, Cyclone V should do much better with more complex designs. How much better depends on the specifics of the design.