Cyclon V performance

It is impossible to give a rule of thumb based only on logic utilization. You can make a very slow system that uses 1% of the FPGA just like a highly optimized and fast system that uses 90%. It is really depending on the design, mostly on what kind of resources are used and the level of pilelining. The main factor will probably be the highest number of LUTs /DSP blocks/memory cells you have in series between two clocked registers.

Given that it is already hard to go over 150MHz in a Cyclone IV without heavy pipelining and optimisation, I wouldn't bet on 250MHz on the Cyclone V.

Just compile your design in Quartus and see what Timequest says.