CYCLON IV GX - ALTGX Won't recieve any valid data

Okay let me clarify.

we chose to use the LVDS standard for the input of our reciever, the signal path is going from fpga# 1 to a pcml -> lvpecl converter to an AC coupled fiber transceiver (the ac coupling is internal.)

after the fiber it goes to another converter from lvpecl to lvds and from that converter with a termination resistor into the rx of fpga# 2

I've added the schematic for you to look.

Ok, thanks, that is clearer.

So you have LVDS DC-coupled into a transceiver receiver channel on a EP4CGX50F484.

The common-mode voltage of LVDS is 1.25V, whereas the common-mode voltage of the receivers is 0.82V. In general I would have recommended AC-coupling these signals. However, "Table 1–2. Electrical Features Supported by the Receiver Input Buffer" in the Cyclone handbook indicates that DC coupling should be ok.

If you probe the signals at those receiver pins, how do they look, and what is the common-mode voltage?

Since you have an external termination, did you disable the on-chip termination (OCT)?

Cheers,

Dave

Hey Dave, the waveforms that come out of the max9376 are really clean and comply with its datasheet, the vcm is indeed 1.25 volts.

we have disabled OCT a long time ago but we will review all of these setting again.

the thing is we checked that the receiver FPGA can differentiate between '1' and '0' on the GXB lines and it does so it seems that using LVDS is fine.

it's a Friday so we're out of the office now, we will check everything Sunday hopefully.

Dave, thank you for all your help so far, we've been stuck on this problem for quite some time and we can use all the help we can get.

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the waveforms that come out of the max9376 are really clean and comply with its datasheet, the vcm is indeed 1.25 volts.

we have disabled OCT a long time ago but we will review all of these setting again.

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The fact that you measure 1.25V means that you have OCT disabled. If you did not, then the termination would be an external 100-Ohms in parallel with two 50-ohms terminated to 0.82V. I would expect that network would have a smaller voltage swing and a different offset voltage.

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the thing is we checked that the receiver FPGA can differentiate between '1' and '0' on the GXB lines and it does so it seems that using LVDS is fine.

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Hang on, you said you could not receive any valid data. If you can differentiate between a 0 and a 1, that is valid data!!! :)

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it's a Friday so we're out of the office now, we will check everything Sunday hopefully.

Dave, thank you for all your help so far, we've been stuck on this problem for quite some time and we can use all the help we can get.

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Talk to you soon then :)

Cheers,

Dave

Hey dave, so we tested the new code, now sending f0 to get a slow repeating signal and yet we still can't get a freq_locked signal.

it seems that it is a physical problem after all..., we have no way to be certain since the signal seems fine.

the bigger problem is we can't ac couple the signal since the board is already built, unless there is some way to do it.

the other thing is that we disabled Rref so we can't use internal termination since it has no refference resistors.

is there anything we can do?

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Hey dave, so we tested the new code, now sending f0 to get a slow repeating signal and yet we still can't get a freq_locked signal.

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Ignore the freq_locked signal for a bit. In your first post you said you were always getting 0xFF. Is that the case now? Can you sometimes gets 0s or 1s? Did you look at the pages from the document I posted? You should reproduce those SignalTap II traces for your own design and confirm that you are reproducing the data sheet recommendations.

Did you check the Altera Knowledge Base for issues with your particular version of software? In Quartus 12.1sp1, freqlocked does not work properly on the Stratix IV series devices. The signal stays high. However, that does not affect the operation of the link, it just means that freqlocked is no use for detecting a broken link.

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it seems that it is a physical problem after all..., we have no way to be certain since the signal seems fine.

the bigger problem is we can't ac couple the signal since the board is already built, unless there is some way to do it.

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I don't see any problem with your LVDS circuit. It should work ok. Do you have another board or another receiver on the same board you can check?

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is there anything we can do?

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Do you have another Cyclone IV GX board you can test? Either one of your custom boards or an Altera kit?

Did you check the power supplies on your receiver channel? Double check to make sure all the voltages are correct.

Cheers,

Dave

-when we ignore freq_locked, we still get a constant ffh,

-we are using quartus 11.1

-we are constantly interchanging the boards to assure this is an issue with the code/ hardware rather than a specific board.

-I checked the datasheet and it seems that while the altgx supports Lvds, it's with an 0.82 vcm so it is probably holding a constant '1', the optical transciever is AC coupled so sending a constant bit will simply disconnect it which is why we thought t he fpga gets valid data.

Is there anything we can do?

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-when we ignore freq_locked, we still get a constant ffh,

-I checked the datasheet and it seems that while the altgx supports Lvds, it's with an 0.82 vcm so it is probably holding a constant '1', the optical transciever is AC coupled so sending a constant bit will simply disconnect it which is why we thought t he fpga gets valid data.

Is there anything we can do?

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This is the root cause of your problem.

You can DC-couple LVDS signals into the OCT, i.e., the *internal* on-chip termination. You cannot use an external termination and DC-couple the signals, because the LVDS signal swing is then 1.25V +/- 200mV (or so), so the minimum LVDS logic level is higher than the receiver common-mode voltage.

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the other thing is that we disabled Rref so we can't use internal termination since it has no refference resistors

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Ok, so OCT needs the RREF resistor. Is there any way you can add an external OCT reference resistor?

If not, then you will have to create your own external termination network such that it looks like a 100-ohm differential termination with a common-mode of 0.82V

These types of networks are commonly used when you need to interface say LVPECL to LVDS. I don't want to spoil your learning experience by pointing you to the answer. See if you can figure it out what I am describing, and let me know if you cannot. Hint: there is a TI app note :)

Cheers,

Dave

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(we also bodged a 2kohm resistor on two vias under the fpga)

now we just need to get the sync right and we can start moving data!

dave, thank you so much, we have been stuck on this issue for two weeks!

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Nice work!

Don't ever get frustrated by these types of problems. These are actually the *best* type of problems to have.

For example, would you have ever read the data sheet properly if you didn't have this issue?

Now when you interface between two standards, you will know to look at the common-mode voltage (and the peak-to-peak voltage).

Good luck with your testing!

Cheers,

Dave

Hey dave, might there be a chance that you help us again?

it seems that now we keep getting random noise on one of the parallel output bits, it keeps chaging where this "noise" appears bit-wise but it is always there, it comes to the point where I send A5 and the receivier gets "A4" constant and then randomly the LSB jumps to '1' for a bit and then falls again.

do you have any idea about this?

thanks again,

Maor.