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Hey dave, so we tested the new code, now sending f0 to get a slow repeating signal and yet we still can't get a freq_locked signal.
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Ignore the freq_locked signal for a bit. In your first post you said you were always getting 0xFF. Is that the case now? Can you sometimes gets 0s or 1s? Did you look at the pages from the document I posted? You should reproduce those SignalTap II traces for your own design and confirm that you are reproducing the data sheet recommendations.
Did you check the Altera Knowledge Base for issues with your particular version of software? In Quartus 12.1sp1, freqlocked does not work properly on the Stratix IV series devices. The signal stays high. However, that does not affect the operation of the link, it just means that freqlocked is no use for detecting a broken link.
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it seems that it is a physical problem after all..., we have no way to be certain since the signal seems fine.
the bigger problem is we can't ac couple the signal since the board is already built, unless there is some way to do it.
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I don't see any problem with your LVDS circuit. It should work ok. Do you have another board or another receiver on the same board you can check?
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is there anything we can do?
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Do you have another Cyclone IV GX board you can test? Either one of your custom boards or an Altera kit?
Did you check the power supplies on your receiver channel? Double check to make sure all the voltages are correct.
Cheers,
Dave
Honored Contributor
