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Altera_Forum
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17 years ago

Creating delay on an internal signal

I have an internal signal on a Cyclone II that I need to delay on the order of several nanoseconds. Best practices and omg-he's using-asynchronous-code aside, what would be the best way to do this? C...
Altera_Forum's avatar
Altera_Forum
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17 years ago

A simple, parameterizable logic cell delay line example goes like this: 

signal delay_line: std_logic_vector(DELAY-1 downto 0);
attribute keep: boolean;
attribute keep of delay_line: signal is true;
begin
gen_delay:
for i IN 1  TO DELAY-1 generate
delay_line(i) <= delay_line(i-1);
end generate;
delay_line(0) <= inp;
outp <= delay_line(DELAY-1);

As discussed in another thread, the method doesn't work with CPLD (apart from MAX II, that is an embedded flash FPGA).