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Forum member Rysc has demonstrated, how to set delay by timing constraints:
http://www.alteraforum.com/forum/showthread.php?t=3068 A delay can also generated manually by inserting logic-cells with a keep attribute. With Cyclone III, 4 to 5 logic cells insert 1 ns delay.
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Fine, but how do I do that if I don't need to bring it out to a pin? I have mostly worked with Xilinx parts in the past, and I have been able to chain IBUFs and OBUFs via internal signals to create delay. Yes, in this case those pins become active, but serve no actual purpose in the design.
Can I assign a constraint between two internal nets and let the router create the delay? That seems to have been the solution in the thread you referenced, but they were applying constraints to pins. I have extra pin locations that I can throw at this problem, but cannot physically make external connections to them.
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