Creating a bidirectional bus

Thanks for your reply. I made the changes you suggested but now Quartus generates this error message: error (10219): verilog hdl continuous assignment error at testusb.v(353): object "inbus" on left-hand side of assignment must have a net type

Line 353 is the assignment to inbus in:

if (read condition) begin

inbus <= USBBUS_i;

end

I made the following changes indicated by <<<<

 
input wire  USBBUS;
wire  USBBUS_i;
reg  USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;   
 
wire  inbus_i;            //<<<<
assign inbus_i = inbus;     //<<<<
 
always @(negedge clk) begin
    if(TXE == 0) begin
        USBBUS_o <= outbus;
        USBBUS_oe <= 1'b1;
    end
    else begin
        USBBUS_o <= 8'hxx;        
        USBBUS_oe <= 1'b0;
    end
    if (RXF == 0) begin
        inbus_i <= USBBUS_i;    //<<<<
    end
end

but that didn't solve the problem

You cannot use a "wire" in an "always" statement. It's a Verilog idiosyncranie.

What people usually do, when dealing with bi-directional signals is to decompose it in 3 variants (input, output and output enable) like this.

input wire  USBBUS;
wire  USBBUS_i;
reg  USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;
always @ (negedge clk) begin
if(write condition) begin
USBBUS_o <= outbus;
USBBUS_oe <= 1'b1;
end
else begin
USBBUS_o <= 8'hxx;
USBBUS_oe <= 1'b0;
end
if (read condition) begin
inbus <= USBBUS_i;
end
end

I rewrote my code as:

output [7:0] USBBUS;

wire [7:0] USBBUS;

reg [7:0] outbus;

wire [7:0] inbus;

always @(negedge clk) begin

if ((TXE == 0)) begin

USBBUS <= outbus;

end

else if ((RXF == 0)) begin

inbus <= USBBUS;

end

else begin

USBBUS <= 8'hz;

end

end

Now my error is: error (10137): verilog hdl procedural assignment error at testusb.v(344): object "usbbus" on left-hand side of assignment must have a variable data type

Any suggestions?