Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI rewrote my code as:
output [7:0] USBBUS; wire [7:0] USBBUS; reg [7:0] outbus; wire [7:0] inbus; always @(negedge clk) begin if ((TXE == 0)) begin USBBUS <= outbus; end else if ((RXF == 0)) begin inbus <= USBBUS; end else begin USBBUS <= 8'hz; end end Now my error is: error (10137): verilog hdl procedural assignment error at testusb.v(344): object "usbbus" on left-hand side of assignment must have a variable data type Any suggestions?