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Altera_Forum
Honored Contributor
13 years agoYou cannot use a "wire" in an "always" statement. It's a Verilog idiosyncranie.
What people usually do, when dealing with bi-directional signals is to decompose it in 3 variants (input, output and output enable) like this.input wire USBBUS;
wire USBBUS_i;
reg USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;
always @ (negedge clk) begin
if(write condition) begin
USBBUS_o <= outbus;
USBBUS_oe <= 1'b1;
end
else begin
USBBUS_o <= 8'hxx;
USBBUS_oe <= 1'b0;
end
if (read condition) begin
inbus <= USBBUS_i;
end
end