Creating a bidirectional bus

Thanks for your reply. I made the changes you suggested but now Quartus generates this error message: error (10219): verilog hdl continuous assignment error at testusb.v(353): object "inbus" on left-hand side of assignment must have a net type

 
input wire  USBBUS;
wire  USBBUS_i;
reg  USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;   
 
wire  inbus_i;            //<<<<
assign inbus_i = inbus;     //<<<<
 
always @(negedge clk) begin
    if(TXE == 0) begin
        USBBUS_o <= outbus;
        USBBUS_oe <= 1'b1;
    end
    else begin
        USBBUS_o <= 8'hxx;        
        USBBUS_oe <= 1'b0;
    end
    if (RXF == 0) begin
        inbus_i <= USBBUS_i;    //<<<<
    end
end