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Altera_Forum
Honored Contributor
Honored ContributorCreate Netlist
Hi,
I want to create a netlist for my design for vhdl sources are not readable by customer. How can I do this? Then, if I want to simulate this netlist. Do I simply instantiate my component? Thanks, Yvan7 Replies
Altera_Forumif you are willing to reverse engineer a design from the Technology Viewer i think you had the time and ability to do the design in the first place.
- Altera_Forum
How unreadable do you need the project to be? any netlist you generate will still be customer readable in the RTL or Technology Map viewer (depending on netlist level) so the customer could reverse engineer your design. Often, your net/register names will be preserved also which may make this process easier.
The only solution: do not provide customers with a partial compile, or have a good NDA in place. - Altera_Forum
i agree with sanmao, use QXP files.
- Altera_Forum--- Quote Start --- I have used VQM files in the past. Quartus can generate a VQM netlist. This is still readable ASCII test but harder to reverse engineer! I believe Altera have moved away from the idea of VQM netlists so you might be best off avoiding them. --- Quote End --- In "Why can't I generate a VQM file in the Quartus II software for certain device families" Altera advices: if you wanted to use a vqm file so that you could send someone your design without sending your source hdl design files, refer to the related solutions section below for better alternatives. The better alternative is here (http://www.altera.com/support/kdb/solutions/rd07312007_549.html).
- Altera_Forum
This is worth a read
http://www.altera.com/support/kdb/solutions/rd07312007_549.html I have used VQM files in the past. Quartus can generate a VQM netlist. This is still readable ASCII test but harder to reverse engineer! I believe Altera have moved away from the idea of VQM netlists so you might be best off avoiding them. - Altera_Forum
Thanks, I will try :)
- Altera_Forum
