Honored ContributorHi,
I want to create a netlist for my design for vhdl sources are not readable by customer. How can I do this? Then, if I want to simulate this netlist. Do I simply instantiate my component? Thanks, Yvan
Honored ContributorHonored ContributorThanks, I will try :)
Honored ContributorThis is worth a read
http://www.altera.com/support/kdb/solutions/rd07312007_549.html I have used VQM files in the past. Quartus can generate a VQM netlist. This is still readable ASCII test but harder to reverse engineer! I believe Altera have moved away from the idea of VQM netlists so you might be best off avoiding them.Honored ContributorHonored Contributori agree with sanmao, use QXP files.
Honored ContributorHow unreadable do you need the project to be? any netlist you generate will still be customer readable in the RTL or Technology Map viewer (depending on netlist level) so the customer could reverse engineer your design. Often, your net/register names will be preserved also which may make this process easier.
The only solution: do not provide customers with a partial compile, or have a good NDA in place.Honored Contributorif you are willing to reverse engineer a design from the Technology Viewer i think you had the time and ability to do the design in the first place.
