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Altera_Forum's avatar
Altera_Forum
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17 years ago

Create Netlist

Hi, I want to create a netlist for my design for vhdl sources are not readable by customer. How can I do this? Then, if I want to simulate this netlist. Do I simply instantiate my componen...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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I have used VQM files in the past. Quartus can generate a VQM netlist. This is still readable ASCII test but harder to reverse engineer! I believe Altera have moved away from the idea of VQM netlists so you might be best off avoiding them.

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In "Why can't I generate a VQM file in the Quartus II software for certain device families" Altera advices:

if you wanted to use a vqm file so that you could send someone your design without sending your source hdl design files, refer to the related solutions section below for better alternatives.

The better alternative is here (http://www.altera.com/support/kdb/solutions/rd07312007_549.html).