CPU instead of USB-Blaster

Question

Moin,

On my design i have a CyclonII (2C35), which normally gets its config from a EPCS16. Programming the EPCS16 can be done by USB-Blaster via the the 2C35. So far no problem.

In addition i have a CPU on that Board, which has some GPIO Pins left, which are connectable to the 2C35's JTAG Pins. Now my question: Is there any documentation available, howto do that "FPGA-Config-through-the-FPGA-into-the-EPCS-via-JTAG-but-without-USB-Blaster"?

Then it would be possible for me to do updates of the FPGA Configuration at the customers site.

I think, JTAG basics won't be the problem, just the altera-specific parts...

Cheers,

WK

altera_forum · Answer

I assume you don't program EPCS through Cyclone, you program it through the Active Serial which linked to both EPCS and FPGA. If you wanna programm EPCS directly from CPU just add it to the AS bus and implement protocol. Read "Serial  configuration devices datasheet" and "configuration" chapter in Cyclone datasheet.

altera_forum · Answer

Moin,

--- Quote Start ---

I assume you don't program EPCS through Cyclone, you program it through the Active Serial which linked to both EPCS and FPGA.

--- Quote End ---

No, unfortunatelly i do not use Active Serial, but definitly JTAG Mode to program the EPCS through the FPGA. So afaik i'd have to load that "Factory Default SFL Image" first into the FPGA, start it and then somehow push my FPGA Config into that SFL Image - right?

Cheers,

WK

altera_forum · Answer

The serial configuration device can be programmed in-system by an external microprocessor using SRunner.

The FPGA can program the serial configuration device in-system using

the JTAG interface with the Serial FlashLoader. This solution allows you

to indirectly program the serial configuration device using the same JTAG

interface that is used to configure the FPGA.

"AN 370: Using the Serial FlashLoader with the Quartus II Software."

altera_forum · Answer

Moin,

Yes, right - AN370 goes into the right direction, but lacks details :) Yes, i have a .jic file, which i want to put into the EPCS via JTAG and the FPGA. That's what i want to do.

But : How exactly do i load e.g. the SFL Image into the FPGA? Which JTAG commands are necessary, (how) is communication between the SFL Image an the USB-Blaster (or in my Case: CPU) to load the contents for the EPCS if the SFL Image is in the FPGA up and running?

Does there exist any available documentation?

Cheers,

WK

altera_forum · Answer

What you try to achieve involves undocumented steps. Programming default SFL image would the most easy and is documented, cause it means performing a FPGA configuration through JTAG from an embedded processor. The embedded JRunner code can do.

The more complicated action is JTAG indirect programming, in other words controlling the SFL through virtual JTAG protocol. Virtual JTAG protocol generally is documented in an application note, the SFL specific protocol part isn't explicitely documented and has to be extracted from the SFL HDL code. Finally you have to perform each step in EPCS programming separately, there's no intelligency built into the SFL design.

For this reason, it's much easier to program an EPCS device at the AS interface directly, as cms mentioned. That's what most people do. Of course, if you didn't connect the interface in your design, you can try indirect JTAG programming. I'm sure, that it can work, but it involves a much higher effort.

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CPU instead of USB-Blaster

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