CPLD Tpd doubt

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Hello

I have a doubt about the cpld's Tpd.

I found the parameters of MAX7000, such as EPM7512, are 7.5ns, 10ns or 12ns. But after compilation, I found that the EPM7512AETC144-12's Tpd is 4.5ns, showing as below:

" Info: 2: + IC(4.800 ns) + CELL(4.500 ns) = 10.300 ns; Loc. = LC12; Fanout = 1; COMB Node = 'delay:inst6|LC_a'"

and I changed the part number as EPM7512AETC144-10, and recomplied, the report as below:

Info: 2: + IC(4.000 ns) + CELL(3.600 ns) = 8.500 ns; Loc. = LC12; Fanout = 1; COMB Node = 'delay:inst6|LC_a'

So for -10 speed devcies, the Tpd is 3.6ns.

Again, change the part number to EPM7256AETC144-5, and the report is below:

Info: 4: + IC(1.700 ns) + CELL(2.200 ns) = 12.400 ns; Loc. = LC9; Fanout = 1; COMB Node = 'delay:inst6|LC_c'

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Hi,

have look into http://www.altera.com/literature/an/an094.pdf. Be aware that tpd is the Pin-to Pin delay, not the Macrocell delay.

Kind regards

GPK

They are basically fixed. Constraints are a means to influence decisions of the synthesis tools, e.g. about different routing pathes.

As you can see from, the datasheet, the CPLD structure is pretty simple. All signal routing goes through the PIA and programmable product terms. It would be possible to create a delay by routing a signal multiple times in and out. It definitely works, when you connect an output pin to the intermediate logic term, but functionally redundant macro cells apparently can't be kept by the CPLD synthesis tool. It obviously ignores the respective synthesis attributes, that are effective in FPGA synthesis.

Of course, it may be the case, that I missed an available method

Hi FvM:

don't optimize away method issue need your help (http://www.alteraforum.com/forum/showthread.php?t=22110)

As shown in above thread, the synthesis attributes you mentioned can run well on CPLD, is new tool version changed?

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P.S.: It would be really helpful not to maintain multiple threads for basically the same topic.

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;) It's my fault!

I strongly want to get the answer!!!!!!:D

It's good, that you showed keep attributes working with CPLD. The trick is to set the global synthesis setting "Ignores LCELL buffers" to "off", which isn't required for FPGA.

However, regarding achieved delay, I don't see additional options to increase it, except for routing the signal in and out of I/O pins. You should also consider, that you don't necessarily increase the delay by using a slower speed grade. The specification is about maximum delay, these devices are designed as logic chips rather than delay lines.