CPLD Tpd doubt

It's good, that you showed keep attributes working with CPLD. The trick is to set the global synthesis setting "Ignores LCELL buffers" to "off", which isn't required for FPGA.

However, regarding achieved delay, I don't see additional options to increase it, except for routing the signal in and out of I/O pins. You should also consider, that you don't necessarily increase the delay by using a slower speed grade. The specification is about maximum delay, these devices are designed as logic chips rather than delay lines.