CPLD Tpd doubt

They are basically fixed. Constraints are a means to influence decisions of the synthesis tools, e.g. about different routing pathes.

As you can see from, the datasheet, the CPLD structure is pretty simple. All signal routing goes through the PIA and programmable product terms. It would be possible to create a delay by routing a signal multiple times in and out. It definitely works, when you connect an output pin to the intermediate logic term, but functionally redundant macro cells apparently can't be kept by the CPLD synthesis tool. It obviously ignores the respective synthesis attributes, that are effective in FPGA synthesis.

Of course, it may be the case, that I missed an available method