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Altera_Forum
Honored Contributor
Honored ContributorConstraints altera cyclone ii
Which is the vhdl syntax to do the placement that i can do in the chip editor to place the logic blocks?
4 Replies
Altera_Forumthank you very very very much!
- Altera_Forum
The syntax for LABs is LAB_Xnn_Ynn, and you can choose a position within a LAB with LCFF_Xnn_Ynn_Znn. If you set a location using the Chip Planner, then look in the .qsf file for an example.
- Altera_Forum
Thank you for your answer.
But the i don't know how assign the location for a logic element or a lut. The only syntax i've found is set_location_assignment PIN_60 -to OUT that is used for the pins. - Altera_Forum
The easiest way is to specify the constraints in a TCL file using "set_location_assignment". I think there may be VHDL attributes that can do it too, but I've never seen that way used.
