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Altera_Forum's avatar
Altera_Forum
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11 years ago

Constrain combinational delay in Timequest

Hi,

I am trying to design an asynchronous system using FPGAs (I know it is not advisable). I need to be able to constrain the combinational delay between a pair of nodes/keepers. Does Quartus provide a command to do this. I am able to generate a custom report and see that the worst case delay in my system is within the limit, but I want the tool to understand during place and route, that I need the delay between certain nodes/keepers to be under a certain value.

Regards

PD

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The command you want would be

    set_max_delay [node1] [ node2] [delay]
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Tricky,

    Can the set_max_delay command constrain the delay between two combinational components. I believe the set_max_delay command modifies the default setup relationship between two FFs

    Regards

    PD
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The whole time constraining system is based around FFs. If you have a purely combinatorial design, then timing analysis is not possible.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You will have to rely on a post fitter timing simulation.

    The problems with a purely combinatorial design is that it will be affected by PVT (process, voltage, temperature) and you cannot perform timing analysis. So every single compile will give you a different result. FPGAs are designed around FF usage, not async design.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks Tricky for the suggestion. However post-fitting timing simulation is an analysis of the circuit once it has been placed and routed. I wish there was a way to direct the place and route. I understand that purely combinatorial designs would be affected by PVT, and that is precisely the reason why I wish to add a constraint, so that my combinatorial delay is within bounds at all corners. I do not wish to sit and manually place the end points of my path. I wish to give the tool a free hand in placing the endpoints of my path anywhere within the FPGA, as long as the delay is within the limit I specify.

    However it seems that this is something that the tool does not do presently.