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Altera_Forum
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11 years ago

Constrain combinational delay in Timequest

Hi, I am trying to design an asynchronous system using FPGAs (I know it is not advisable). I need to be able to constrain the combinational delay between a pair of nodes/keepers. Does Quartus p...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You will have to rely on a post fitter timing simulation.

The problems with a purely combinatorial design is that it will be affected by PVT (process, voltage, temperature) and you cannot perform timing analysis. So every single compile will give you a different result. FPGAs are designed around FF usage, not async design.