Constrain combinational delay in Timequest

Thanks Tricky for the suggestion. However post-fitting timing simulation is an analysis of the circuit once it has been placed and routed. I wish there was a way to direct the place and route. I understand that purely combinatorial designs would be affected by PVT, and that is precisely the reason why I wish to add a constraint, so that my combinatorial delay is within bounds at all corners. I do not wish to sit and manually place the end points of my path. I wish to give the tool a free hand in placing the endpoints of my path anywhere within the FPGA, as long as the delay is within the limit I specify.