Connection Setup for JTAG - simplification

This really got me thinking.

FPGA pins tend to be limited, so it's not great if you have to dedicate pins for example to JTAG, as that's 4 less I/Os available.

So there is the pin JTAGEN, when high forces 4 I/O pins to be JTAG (TDI,TDO, TMS, TCK).

But the JTAGEN pn can be used as user I/O.

Or if JTAGEN=0 the 4 "JTAG" I/O can be used as normal I/O.

There is a config bit to "Enable JTAG pin sharing". I wonder what this does internally?

If as in your case you are using JTAGEN as user I/O, to use the JTAG pins, do you need to temporarily force JTAGEN high or is this unnecessary? Possible NO only if JTAG pin sharing is disabled???

If JTAG pin sharing is enabled then foir sure you need to force JTAGEN high during programming in order for the JTAG pins to work.

What I was working towards is that during "mission mode" operation, if JTAG pins were to toggle then the TAP (internal IP which is controlled by the JTAG pins) would operate and could possibly corrupt the programmed state of the device.

I used a chip where it was recommended (i.e. must do it) to pull the JTAG reset pin (TRST - which many chips have) low to hold the TAP in reset. The concern was that unintentional toggling of TCK and other JTAG pins could cause the device to go into test mode! Floating pins can in theory see false data depending upon whether there are wires close to other toggling wires (cross coupling).

So I am now thinking that if the "JTAG Pin Sharing" config bit is set to disabled, the JTAGEN pin is totally disconnected from the internal circuitry.

Also if "JTAG Pin Sharing" config bit is enabled it likely goes to the select of 4 muxes where the "A" inputs connect the pads to internal user I/O and the "B" inputs connect the pads to the internal JTAG circuitry.

More assumptions, if "JTAG Pin Sharing" is enabled and JTAGEN is low (for user I/O pins), the the internal connections to the TAP (from the "JTAG" pads) will be forced to a known safe value (probably '0').

=> So IF you have the above scenario, I suspect that you can get away with no external pull ups/downs on the JTAG pins since it will be managed internally.

"The JTAG pin sharing is disabled, so i will use JTAGEN pin as usual USER I/O pin. Can i in this case leave all JTAG pins floating, so no pull up/down resistor on JTAG lines are required?"

So in this case I agree that you need to use pull ups/downs on the dedicated JTAG pins to avoid any operation of the TAP during "mission mode" by pulling them to a known inactive state.