Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Connect 4 async SRAMs to FPGA

Hello

this is rather a hardware question.

I´d like to connect 4 asyncrone SRAM devices (250MHz NoBL Types) to a Cyclone IV FPGA.

Each data signal is a point to point connection FPGA to SRAM with an impedance of 50ohm. So far so good.

The question is, how to connect CLK and address lines. As each address line has to be splitted into 4 lines to run to the SRAM devices. Where should i split the trace. Just when it comes out of the FPGA? Or somewhere else? How to terminate the several traces.

A simple way would be to connect each SRAM with its own CLK and address lines from the FPGA. For this solution there are not enough pins on the FPGA. At least the device I´d like to use.

So has anyone experience in suche designs or solution for me. :confused:

Thanks Robert

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Generally speaking you would split the traces at the driver end (the FPGA in this case). You could add a series resistor in each branch (at the driving end) for "series" termination. Alternately, you could externally buffer each set of address/clock lines, which adds up to a lot of buffers. At 250Mhz I would certainly buffer each clock signal independently for maximum signal integrity, or you could use four FPGA outputs for clocks. If your clock is generated from a PLL in the FPGA, check the worst case jitter specification which can be quite high.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Thank you for your reply. I´d like to use a Cyclone iV device (EP4CE55F23C7N). There are 4 PLLs available. I will need one PLL for LVDS interface (camera) and one PLL for clock recovery from that LVDS device. So there are only two PLLs left. Therefore it will not be possible to drive each clock with one PLL output. And there is only one PLL out from each PLL - as far as I understood. So an external clock driver is a good idea. Even more I can shift the clock phase with the PLL.

    For the address lines I will add two 25ohms resistors after splitting the signal out of the FPGA near the FPGA driver pin. As i also want to use OCT feature (50ohm impedance). Is that OK?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Why "two 25ohm resistors"? I thought you had four SRAM chips. You would want a resistor in each branch. OCT may or may not help, it's not the same as a resistor in each branch. In any event you can enable/disable the OCT as desired.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    There are two resistors because I want to use one signale set (addr, WEn, OEn, etc.) for two SRAMs. A second signal set is for the other two SRAMs.

    So if I have to drive two address lines with one FPGA pin i think there should be one 25ohm resistor in each address line.