Connect 4 async SRAMs to FPGA

Generally speaking you would split the traces at the driver end (the FPGA in this case). You could add a series resistor in each branch (at the driving end) for "series" termination. Alternately, you could externally buffer each set of address/clock lines, which adds up to a lot of buffers. At 250Mhz I would certainly buffer each clock signal independently for maximum signal integrity, or you could use four FPGA outputs for clocks. If your clock is generated from a PLL in the FPGA, check the worst case jitter specification which can be quite high.