Forum Discussion
AdzimZM_Altera
Regular Contributor
2 years agoHi,
I think the calibration should be okay.
There is a sequencer that will calibrate the memory interface with the memory device.
The purpose of the EMIF IP should be the same which is to perform read or write transaction.
I think the idea of your prototype is looks okay.
Maybe you can try in simulation first.
For the devices, DDR4 protocol is supported by Arria 10, Stratix 10 and Agilex devices.
If you go to EMIF IP Support Center page, there is a device selector tool that you can use to check the performance of the devices.
You may refer to that link for EMIF related resources.
It's may not contains everything but you can ask here if you have any question about the EMIF IP.
Regards,
Adzim