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Mehdi1234's avatar
Mehdi1234
Icon for New Contributor rankNew Contributor
2 years ago

Configuring DDR4 interface as Slave

Can DDR4 interface be configured as Slave. I want to make a FPGA based NV memory device having a similar electrical/protocol interface as SDRAM which means configuring the DDR4 interface of the FPG...
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AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Thank you for submitting you question in Intel Community.

I'm Adzim will assist you in this thread.


The DDR4 EMIF IP can be configured as Hard PHY Only and Hard PHY and Hard Memory Controller.

If you intended to use your own memory controller, then you can generate the Hard PHY Only DDR4 EMIF IP.


The DDR4 EMIF IP is used AFI.

DFI is not officially supported by Intel.


Regards,

Adzim


  • Mehdi1234's avatar
    Mehdi1234
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi Adzim,

    Thanks for the help.

    When DDR4 EMIF IP is configured as hard PHY Only, can it be used be used as a Slave? Do you anticipate any issues with caIibration?

    I like to make a simple prototype as shown below. Do you think this is possible? I don't need that much logic; just the AFI to block ram interface and some block RAM for testing. Which FPGA do you recommend; Stratix, Arria, or something else. I only need 8 lanes of DDR4. For prototype, I can even use DDR3.