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Right, but its not working. So as a debugging aid, can you control the chip select signal?
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Yes I can control the chip select. I'll certainly give that a try, set CS high during power up and then set it low after a few clock cycles.
What bothers me is I never fail to read the correct default value of a register. For now I have to change the address value in my VHDL code, re-compile the code, and re-program the FPGA. I would think a read would be more difficult to accomplish since the SDIO line has to change from an input to an output whereas for a write, it stays as an input line.
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