Config issue Cyclone IV (EP4CE6U14I7N)

Hi,

is the design using a on chip clock (as many FPGA designs due) to run? Thus check whether the System clock is active.

Additionally I'd try a very simple design like clock divider and check if this runs to exclude physical damage to the chip...

The SPI device shouldn't have any influence on chip if configured with JTAG, thus I'd start with JTAG I/F, Auto detect (to check JTAG chain ok), ...

KR

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We have problems to get a new design configured.

The programmer (PC application launched from Quartus II) tells that we succeed, but CONF_DONE is not released on the target.

JTAG and AS-mode gives the same result - green Successful sign, but no system in active mode.

We have tested with different Quartus versions.

The last tests running Quartus II 64-bit ver. 12.1.

We haven't forgot to check options for DEV_OE etc.

The hardware interface is according to Altera standard, with pullup/pulldown resistors etc.

Core voltage and bank voltages are correct.

MSEL0=L, MSEL=L, MSEL2=H

The SPI-flash used is 25P28V6P (a 128MBit type).

It is not an Altera/Intel-labeled device, but no other types were available for this fast protype.

I haven't measured waveforms during serial transfer yet.

I have never seen such problems before.

Any idea would be helpful.

Thanks in advance.

/Pär

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UPDATE :

JTAG problem was project related, now working.

AS still NOT working.

"Disable EPCS ID Check" is checked (took a while to find a Quartus version with this feature working, not working in 12.0 and 12.1).

My only guess is that the SPI flash (25P28V6P) is not is supported by the Cyclone IV.

I will now test this one instead : MT25QL128ABA8ESF-0SIT

i would be grateful for comments on this...

To find a config memory is always tricky. You can easily find 10 tables with compatible devices on the web, but all devices obsolete.

Recommended EPCS works, but no devices were available when our prototype was assembled.

I have never understood Alteras strange behavior regarding pricing, especially on EPCS - with a standard list price of $100000000000.

What else have you got connected to CONF_DONE? Is anything else holding it low? The FPGA will not start until CONF_DONE is released, whether the FPGA's internal state machine is holding it low or external circuitry.

When you say AS is reported as successful, what are you doing exactly? Programming the serial flash via JTAG? Can you program the serial FLASH device?

I suggest you focus on configuring the FPGA directly using JTAG mode until something is working.

Check all your power rails and ensure that all power pins are connected correctly. Expect strange behaviour if one power pin is not connected correctly.

Cheers,

Alex

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What else have you got connected to CONF_DONE? Is anything else holding it low? The FPGA will not start until CONF_DONE is released, whether the FPGA's internal state machine is holding it low or external circuitry.

When you say AS is reported as successful, what are you doing exactly? Programming the serial flash via JTAG? Can you program the serial FLASH device?

I suggest you focus on configuring the FPGA directly using JTAG mode until something is working.

Check all your power rails and ensure that all power pins are connected correctly. Expect strange behaviour if one power pin is not connected correctly.

Cheers,

Alex

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CONF_DONE pin has only a pullup resistor connected, only the FPGA can force it low.

I can program and verify the serial FLASH from the Programmer.

I guess the USB-blaster "can handle the device", but not the FPGA.

What more to tell?

The "Disable EPCS ID Check" option is selected (since the device isn't an EPCS-type)

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I can program and verify the serial FLASH from the Programmer.

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Is this via the FPGA, using indirect programming (a .jic file) or do you have a separate programming header connected directly to the serial FLASH device? - see Figure 8-6, page 8-20 of the 'configuration and remote system upgrades in cyclone iv devices (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-5v1.pdf)' section of the handbook.

If it's the former (using a .jic file) then I'm stumped - unless you're simply using the wrong .sof file to generate your .jic file.

If the latter, using a separate programming header, then you need to re-check your connections from serial FLASH to FPGA. 'All' the FPGA does to configure from the serial FLASH is assert chip select (nCSO) and generate a clock. This is the simplest form of access to a serial FLASH device. So, I don't think there's any chance the FPGA isn't able to 'handle the device'.

I'm guessing you mean a Micron '25P128V6P'. I've not used that exact serial FLASH device before but I have used plenty, successfully, from that family of parts.

Cheers,

Alex