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Altera_Forum
Honored Contributor
Honored ContributorConfig issue Cyclone IV (EP4CE6U14I7N)
We have problems to get a new design configured. The programmer (PC application launched from Quartus II) tells that we succeed, but CONF_DONE is not released on the target. JTAG and AS-mode ...
Altera_ForumHonored Contributor
Honored ContributorHi,
is the design using a on chip clock (as many FPGA designs due) to run? Thus check whether the System clock is active. Additionally I'd try a very simple design like clock divider and check if this runs to exclude physical damage to the chip... The SPI device shouldn't have any influence on chip if configured with JTAG, thus I'd start with JTAG I/F, Auto detect (to check JTAG chain ok), ... KR
