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Altera_Forum's avatar
Altera_Forum
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16 years ago

Config Done Fails to Go high with simple SOF file(Jtag+USB Blaster)

Hello All,

Finlay we have got our boards and started testing them out... We were able to successfully Detect the Cyclone 3 120 chip and run Jtag Debug tests, but not been able to configure the chip successfully as of yet.

After reading allot on Alteras documentation and this forum , I have not found anything which has solved my problem.

We are using the Combined Jtage/AS config setup, and have confirmed that we have met all the rules of Week pull up and down resisters and etc but yet we continue to get an error stating config done failed to go high..

The Programmer fails also when i try to just dump an simple SOF file on the FPGA , without bothering to dump programming files onto the AS device.

I was wondering , is it oka for me to rule out a problem with the Jtag interface, considering the fact that the it successfully detects the chip and the Run iteration test does not have any errors?

If not then how else can i debug whats wrong, as now our team is hitting a dead end.

hope to hear from you all,

regards Nadeem

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    We are using the Combined Jtage/AS config setup

    --- Quote End ---

    The reported situation isn't completely clear to me. You should tell, what's the exact hardware configuration, e.g. referring to an Altera schematic.

    In some situations, it's necessary to deactivate the on-chip configuration controller to assure, that the JTAG configuration isn't disturbed by tries to load an AS configuration. It's a Quartus Programmer option, that should be selected.

    If basic JTAG configuration still fails (config done fail), it's most likely a hardware problem.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    your usb blaster connection confuses me a bit

    why ist pin 6 connected to nCE instead of Vio ?

    why did you connect pin 2 TDO to Pin 6 also what is not connected normaly ?

    i am quite not shure if you have connected the jtag signals to vcca (2,5V) instead of 3,0 or 3,3V ...

    as the epcs device can be programmed via jtag over an minimal nios design, we haven't placed the as interface anymore.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    As said, it's not according to the Altera schematics to connect nCE at the JTAG header. It's only used in the direct AS programming configuration. But I don't expect, that it would disturb JTAG operation. Apart from this point, the circuit seems correct.

    Using 2.5V versus 3.0 or 3.3V for the JTAG interface is basically a question of avoiding overshoots at the FPGA, JTAG operation, including device configuration should be still possible.

    As you observed DCLK activity, deactivation of the on-board configuration controller should stop it.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    as the vcio has been connected to nCE instead of a supply voltage, could it be that this pin does not provide enough current for the io of the usb blaster ? it is just an idea that this not low impedance supply could have an effect on the driver side between usb blaster (JTAG) and the target....

    also i still try to recover why i have in mind that my fae told me that i must use vcca=2,5V and must not use 3,0v i also have in my design to aviod 3,3V signal problems cyclone 3 can have ...
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Pin 6 isn't VCIO at UBS-Blaster, it's an nCE output for AS programming.

    VCCA must be supplied from 2.5V, but it's not absolutely required to operate the JTAG interface at VCCA. It's suggested in the Device Handbook to get a higher margin to maximum voltage ratings. If your circuit is using other protection means at the JTAG interface, e.g. clamp diodes, it's fine with 3.3V.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hello Alll,

    Thanks Allot for replying my thread.. Both of you were right , I finally realized after reading the documentation again , that the hardware engineer had connected the nCE pin to the jtag interface when really it was to be connected to ground and pin 6 of jtag left unconnected, for in system programming.

    Finally we have got the board to configure successfully with a SOF file, however still having problems programming the epcs.

    The error we get now is : error:" cant recognize silicon ID "when using the Qaurtus programmer and No epcs on board layout in Niose , using flash programmer.

    any suggestions about what must be wrong.

    regards nadeem
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    do you try to programm the epcs via the jtag or via your IS programming connector ?

    what messages do you get ?

    have you checked your quartus settings ? in nios forum i had posted my settings for c3 and epcs that i had to add to the project qsf file.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes We are using IS, and all the setting have been checked multiple times..

    the error we are getting is :- Error :Can't recognize silicon ID .

    This error apears when trying to load up the Jic file into the epcs using IS.

    regards nadeem
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    as your are using EPCS64 and not a manufacture other than altera the system should know the ID, so no overide file needed here

    the thing with the id could be that it always reads 1 or 0

    if your schematic is a mentioned in altera doc, have you tried to download a dummy nios design via jtag ? just nios + epcs controller and on chip mem to satisfy sopc. this dummy design is only used to be downloaded via jtag to give a running nios cpu and then via command line you can try to reach the epcs via nios and hopefully programm it.

    the command line also gives some debug infos.

    if the epcs always gives 0 or 1 then recheck all signals. try to monitor the epcs via scope to see if it respons (understands the commands)