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Altera_Forum
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17 years ago

Config Done Fails to Go high with simple SOF file(Jtag+USB Blaster)

Hello All, Finlay we have got our boards and started testing them out... We were able to successfully Detect the Cyclone 3 120 chip and run Jtag Debug tests, but not been able to configure the ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

As said, it's not according to the Altera schematics to connect nCE at the JTAG header. It's only used in the direct AS programming configuration. But I don't expect, that it would disturb JTAG operation. Apart from this point, the circuit seems correct.

Using 2.5V versus 3.0 or 3.3V for the JTAG interface is basically a question of avoiding overshoots at the FPGA, JTAG operation, including device configuration should be still possible.

As you observed DCLK activity, deactivation of the on-board configuration controller should stop it.