Honored ContributorHi
I wrote a siple program in vhdl to implement an AND gate. Just as a start. I need to know how we compile the code/project. I tried and it's giving me an error saying entity names must be the same. :confused: Also, which file should I add in the project to make the project complete, e.g. .vhd, .txt, .tdf, .scf, etc? Your assistance would greatly be appreciated. :) Thx R
Honored ContributorFirst step - stop using Maxplus 2. its over 10 years old, and VHDL support is very poor. Try downloading the new version of quartus.
Secondly, if the project is VHDL, you only need to add the .vhd files.Honored Contributorhelp:cry:
I have circuit an transmitter serial asynchronous and I to write VHDL code here is the schema But there are problems: How to write VHDL comprehensive program to operate our circuit I have a program but it gives me the error here is theHonored Contributor:cry:
How to write VHDL comprehensive program to operate our circuit I have a program but it gives me the error here is theHonored ContributorI suggest you start your own thread rather than hijacking someone elses.
Honored Contributori'm very sorry
