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Altera_Forum's avatar
Altera_Forum
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15 years ago

Compiling vhdl project using Maxplus II

Hi I wrote a siple program in vhdl to implement an AND gate. Just as a start. I need to know how we compile the code/project. I tried and it's giving me an error saying entity names must be the sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

First step - stop using Maxplus 2. its over 10 years old, and VHDL support is very poor. Try downloading the new version of quartus.

Secondly, if the project is VHDL, you only need to add the .vhd files.