Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Compiling vhdl project using Maxplus II

Hi I wrote a siple program in vhdl to implement an AND gate. Just as a start. I need to know how we compile the code/project. I tried and it's giving me an error saying entity names must be the sa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

:cry:

How to write VHDL comprehensive program to operate our circuit

I have a program but it gives me the error here is the