compile the same project several times get several different timing results, why?

Question

In my project, the original files are top.vhd, Niosii_cpu.sopcinfo, Niosii_CPU.sopc, create-quartus-project.tcl , board.tcl file (which includes setting configuration), board.sdc (which include timing constraint file), all other project files are created by make files based on original files. I use quatus 11.1 (builder 173 ) to compile, place route. After a try, I get a timing report, then I revert the whole project to original files, also delete all temperary files.  I compile again, I would get different timing result. I have tried 5 times, the worst setup slack is 0.247, 0.124, -0.973, -0.074, -0.346 ns. I'm confused by the compilation. Why does the  timing result varies so much? I'm trying to increase some slack by setting fitter, it is hard to see my modification effect if the timing varies so much at the first place. Does anybody have any sugguestion?

altera_forum · Answer

Compiling from a given set of files with a given seed on a given platform is supposed to give the same results each time. Are you sure nothing is changed on each compile?

Do you re-generate the Sopc system at each compile? Do you have a system id component? If yes it may produce a slightly different result on each generation, as the timestamp will be different.

altera_forum · Answer

--- Quote Start ---

Compiling from a given set of files with a given seed on a given platform is supposed to give the same results each time.

--- Quote End ---

I have also noticed random results starting in Quartus 11.1sp1 or so. In the Qsys PCIe tests in this thread:

http://www.alteraforum.com/forum/showthread.php?t=35678

Quartus 11.0 gives the same number of resources each synthesis run, whereas 11.1sp1 and 11.1sp2 give different results. Synthesis scripts in the project zip file can be used to regenerate the designs.

I agree that this is an annoying feature. The whole point of having the seed is so that the user can choose when to randomize the synthesis.

Cheers,

Dave

altera_forum · Answer

Yes, it regenerate sopc system each compilation, and there is system id component in the sopc system.

I run a make file which generate project file, generate sopc system and compile. Each time I run the make file (before next compilation, all generated files are deleted), it gives different timing result.

In order to check it is the matter of regeneration of sopc system or not.

I open the generated project file in Quatus (all generated files are kept), I recompiled by double click compilation design in Quatus GUI. The timing result is still different with previous result which is compiled by make script. But if I recompile in Quatus GUI again, it will stay the same. I do not understand, are there any difference between Quatus GUI and script command?

By the way, I installed quatus 11.1, I do not install service pack 1, but the builder is 173.

altera_forum · Answer

Another variable I noted is that if you generate timestamp then it changes timing results while nothing else has been changed. It is all to do with the huge fitting space available to the fitter.

altera_forum · Answer

--- Quote Start ---

Another variable I noted is that if you generate timestamp then it changes timing results while nothing else has been changed. It is all to do with the huge fitting space available to the fitter.

--- Quote End ---

In my example, there are no changes whatsoever to any design files. Quartus 11.0 consistently produces identical resource results, whereas 11.1sp1 and 11.1sp2 produce different resource results (and timing).

Something in the router logic definitely changed in the latest versions. The change was for the worse in my case, as the Qsys PCIe designs no longer meet timing, whereas they did in 11.0.

Cheers,

Dave

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compile the same project several times get several different timing results, why?

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