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Altera_Forum
Honored Contributor
Honored Contributorcompile the same project several times get several different timing results, why?
In my project, the original files are top.vhd, Niosii_cpu.sopcinfo, Niosii_CPU.sopc, create-quartus-project.tcl , board.tcl file (which includes setting configuration), board.sdc (which include timin...
Altera_ForumHonored Contributor
Honored ContributorCompiling from a given set of files with a given seed on a given platform is supposed to give the same results each time. Are you sure nothing is changed on each compile?
Do you re-generate the Sopc system at each compile? Do you have a system id component? If yes it may produce a slightly different result on each generation, as the timestamp will be different.
