Forum Discussion
Altera_Forum
Honored Contributor
14 years agocompile the same project several times get several different timing results, why?
In my project, the original files are top.vhd, Niosii_cpu.sopcinfo, Niosii_CPU.sopc, create-quartus-project.tcl , board.tcl file (which includes setting configuration), board.sdc (which include timin...
Altera_Forum
Honored Contributor
14 years agoI am not familiar with scripting but I assume it will call project settings from qsf. When you click on GUI the qsf will be updated by whatever setting are there (default or otherwise).
However, I will address your problem differently. When timing is marginal then you get get violations migrating from place to place depending on many many variables in the project or code. The change of seed is one of them and is only practical at final sign off. The remedy during development is to see if there is any pattern of timing violations i.e. a bottleneck that can be improved.