compile the same project several times get several different timing results, why?

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Another variable I noted is that if you generate timestamp then it changes timing results while nothing else has been changed. It is all to do with the huge fitting space available to the fitter.

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In my example, there are no changes whatsoever to any design files. Quartus 11.0 consistently produces identical resource results, whereas 11.1sp1 and 11.1sp2 produce different resource results (and timing).

Something in the router logic definitely changed in the latest versions. The change was for the worse in my case, as the Qsys PCIe designs no longer meet timing, whereas they did in 11.0.

Cheers,

Dave