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Altera_Forum's avatar
Altera_Forum
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13 years ago

compile the same project several times get several different timing results, why?

In my project, the original files are top.vhd, Niosii_cpu.sopcinfo, Niosii_CPU.sopc, create-quartus-project.tcl , board.tcl file (which includes setting configuration), board.sdc (which include timin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Another variable I noted is that if you generate timestamp then it changes timing results while nothing else has been changed. It is all to do with the huge fitting space available to the fitter.