code style for mixed width port dpram

hi,everybody.How to modify this code to generate a mixed width port dpram,

the simplest example such as :

emodule true_dpram_sclk

(

input [7:0] addr_a,

input [0:0] data_a,

input [4:0] addr_b,

input [7:0] data_b,

input we_a, clk,

output reg q_a,

output reg [7:0] q_b

);

// Declare the RAM variable

reg [0:0] ram[63:0];

// Port A

always @ (posedge clk)

begin

if (we_a)

begin

ram[addr_a] <= data_a;

q_a <= data_a;

end

else

begin

q_a <= ram[addr_a];

end

end

// Port B

always @ (posedge clk)

begin

q_b[0] <= ram[{addr_b,3'd0];

q_b[1] <= ram[{addr_b,3'd1];

q_b[2] <= ram[{addr_b,3'd2];

q_b[3] <= ram[{addr_b,3'd3];

q_b[4] <= ram[{addr_b,3'd4];

q_b[5] <= ram[{addr_b,3'd5];

q_b[5] <= ram[{addr_b,3'd6];

q_b[7] <= ram[{addr_b,3'd7];

end

endmodule

///////////////////

This code works ok,but it get more alms and other resources in ep2sxx .

When i used Megawizard to generate the same funciton LPM,and it just waste one m4ks.

Now the situations is i can't used the LPM code,how can i changer my verilog code style get the the same result of LPM. Please help.thanks a lot!

The reference code is :

emodule true_dpram_sclk

(

input [7:0] data_a, data_b,

input [5:0] addr_a, addr_b,

input we_a, we_b, clk,

output reg [7:0] q_a, q_b

);

// Declare the RAM variable

reg [7:0] ram[63:0];

// Port A

always @ (posedge clk)

begin

if (we_a)

begin

ram[addr_a] <= data_a;

q_a <= data_a;

end

else

begin

q_a <= ram[addr_a];

end

end

// Port B

always @ (posedge clk)

begin

if (we_b)

begin

ram[addr_b] <= data_b;

q_b <= data_b;

end

else

begin

q_b <= ram[addr_b];

end

end

endmodule