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Altera_Forum's avatar
Altera_Forum
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9 years ago

Clocking MAX10 and ADC at same 125 MHz frequency

I am designing a system with a MAX10 and a 125 MSPS ADC with LVDS, and I'm wondering how to handle the clocks.

My plan is to clock both at 125 MHz and treat them as different clock domains, but the question is if I need to have two oscillators, or if I can use the dedicated clock output from the MAX10 to clock the ADC. Maybe that's too noisy?

I don't want to use the clock outputs from the ADC to clock the MAX10, because I want to be able to put the ADC in low-power mode from the MAX10 and just run that some of the time to conserve power.

I could use two oscillators or a discrete clock buffer, but both those solutions (especially the latter) seem wasteful in terms of power.

ADC: LTC2261IUJ-12

Oscillator: DSC1103DL5-125.0000T

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The answer depends on your application. If it's relying on spectral purity of the ADC signal, e.g. RF or similar signal analysis applications, the ADC must be clocked directly from a low jitter source. Otherwise using a FPGA PLL generated ADC clock might be acceptable.

    Thinking a bit about the data processing scheme, it should be clear that the FPGA needs a common clock source with the ADC at least for the ADC interface. Unless your application requires a second asynchronous clock source, it's pretty straightforward to use the 125 MHz as FPGA clock or derive other clocks in a synchronous manner.

    A minimal design would simply feed the LVDS clock to both devices. Should be possible without buffers.
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    As I see it, the it would need to be a common clock if the ADC was running continously, but I'm sleeping it some of the time and only running it in bursts. To avoid any timing issues I'm treating them as asynchronous and synchronizing the ADC clock to the core clock in the FPGA.

    I think I will try your minimalist suggestion. Input capacitance for FPGA and ADC is only around 10 pF total.

    Thanks!
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    The common clock should as a party line with end termination.

    If you don't need very low ADC phase noise, a lower oscillator frequency and ADC clock generation in FPGA can achieve lower overall power consumption.