Clocking MAX10 and ADC at same 125 MHz frequency

The answer depends on your application. If it's relying on spectral purity of the ADC signal, e.g. RF or similar signal analysis applications, the ADC must be clocked directly from a low jitter source. Otherwise using a FPGA PLL generated ADC clock might be acceptable.

Thinking a bit about the data processing scheme, it should be clear that the FPGA needs a common clock source with the ADC at least for the ADC interface. Unless your application requires a second asynchronous clock source, it's pretty straightforward to use the 125 MHz as FPGA clock or derive other clocks in a synchronous manner.

A minimal design would simply feed the LVDS clock to both devices. Should be possible without buffers.