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Altera_Forum's avatar
Altera_Forum
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9 years ago

Clocking MAX10 and ADC at same 125 MHz frequency

I am designing a system with a MAX10 and a 125 MSPS ADC with LVDS, and I'm wondering how to handle the clocks. My plan is to clock both at 125 MHz and treat them as different clock domains, but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

As I see it, the it would need to be a common clock if the ADC was running continously, but I'm sleeping it some of the time and only running it in bursts. To avoid any timing issues I'm treating them as asynchronous and synchronizing the ADC clock to the core clock in the FPGA.

I think I will try your minimalist suggestion. Input capacitance for FPGA and ADC is only around 10 pF total.

Thanks!