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Altera_Forum
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9 years ago

Clocking MAX10 and ADC at same 125 MHz frequency

I am designing a system with a MAX10 and a 125 MSPS ADC with LVDS, and I'm wondering how to handle the clocks. My plan is to clock both at 125 MHz and treat them as different clock domains, but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The common clock should as a party line with end termination.

If you don't need very low ADC phase noise, a lower oscillator frequency and ADC clock generation in FPGA can achieve lower overall power consumption.