Clock synchronization across 1Msps ADCs

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I'm hoping some of you might prod me in the right direction. I'm looking to synchronize a large number of ADC channels going into an FPGA. The sampling rate is high (~1MSPS), but doesn't quite require using an ADC with the JESD204 standard. Data sample synchronization is critical and therefore clock skew and jitter must be minimized.

I intend on keeping all board clock/sync lines at the same length. Should I also be using a PLL to generate this synchronous clock/sync, or use an onboard oscillator with clock distribution buffers? Is there another topology that might work better?

What if I were to need multiple FPGAs, how would you synchronize between multiple devices?

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What kind of flexibility do you have with regards to the input signals to each ADC? One method of synchronizing ADCs that works nicely is to have a common signal that can be switched into each ADC and any analog electronics.

For example, a noise signal with a bandwidth over DC to 500kHz can be sampled by your ADCs. The cross-correlation of that data is ideally a delta function, with a cross-power spectrum that has flat phase.

Any delay will show up as a shift in the delta function peak, or slope in the spectrum. You can compensate for the measured delay using a fractional-delay-line (basically a FIR filter with asymmetric taps).

For clock generation and distribution, the skew is of no consequence when you calibrate using a noise source. The jitter of the clock is critical in maintaining the dynamic range of the ADC. How many bits are you trying to get out of your ADC? You should be able to use clock distribution buffers.

If the jitter from the FPGA PLL output clocks at 1MHz is acceptable for your dynamic range, then you could align ADC clocks using the PLL delay shift features. I use external DDSes for this in my applications, eg., see the docs here

http://www.ovro.caltech.edu/~dwh/carma_board/

Cheers,

Dave

Hi Dave,

Yes, I have the flexibility to calibrate across all channels simultaneously. I'm planning to design this feature into it for my own sanity! So, it would be a feasible option to correct for any delays after the board is fabricated. I would not want to introduce FIR filters in my FPGA for each channel unless absolutely necessary, though. Worst case scenario, the data could be collected with the FPGA and post-processed offline where computational load isn't a hard requirement. This would unfortunately preclude me from doing any processing on-board in realtime.

I'm looking at fairly high dynamic range (16-24 bits, differential inputs), but more important than dynamic range is phase matching across channels. I will need to look closely at my jitter requirements to make sure the PLL can meet this. Otherwise, DDS may be a better approach as you suggested.

I appreciate you sharing the CARMA board. It's a neat application. I'll have a closer look today at how you approached the problem. There's certainly some things I can learn from it!

-Jason

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I'm looking at fairly high dynamic range (16-24 bits, differential inputs), but more important than dynamic range is phase matching across channels.

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The dynamic range of your signal will be limited by the clock jitter. The limit on the jitter can be estimated from the amplitude error you get when sampling a sinusoid with a clock that has jitter. Take a look in the data conversion handbook, edited by Walt Kester (newnes, 2005), p2.71 and p2.72

http://www.analog.com/library/analogdialogue/archives/39-06/data_conversion_handbook.html

and p17

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)

An ideal 16-bit converter an SNR_Q of about 6dB x 16 = 96dB, whereas a 24-bit converter has an SNR_Q of about 6dB x 24 = 144dB.

Look at the plot on p2.72 of Kester, at your 1MHz sampling rate, your jitter needs to be lower than 1ns for 16-bit operation and lower than a few 10s of femtoseconds for higher resolution.

Your design difficulty will be in achieving low jitter. So, determine if that really is a requirement first.

Cheers,

Dave