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I'm looking at fairly high dynamic range (16-24 bits, differential inputs), but more important than dynamic range is phase matching across channels.
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The dynamic range of your signal will be limited by the clock jitter. The limit on the jitter can be estimated from the amplitude error you get when sampling a sinusoid with a clock that has jitter. Take a look in
the data conversion handbook, edited by Walt Kester (
newnes, 2005), p2.71 and p2.72
http://www.analog.com/library/analogdialogue/archives/39-06/data_conversion_handbook.html and p17
http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (
http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)
An ideal 16-bit converter an SNR_Q of about 6dB x 16 = 96dB, whereas a 24-bit converter has an SNR_Q of about 6dB x 24 = 144dB.
Look at the plot on p2.72 of Kester, at your 1MHz sampling rate, your jitter needs to be lower than 1ns for 16-bit operation and lower than a few 10s of femtoseconds for higher resolution.
Your design difficulty will be in achieving low jitter. So, determine if that really is a requirement first.
Cheers,
Dave
Honored Contributor
